VLSI Physical Design
VLSI Physical Design
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Algorithmic Level Techniques for Low Power Design
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Видео

Summarization of the Course
Просмотров 8 тыс.7 лет назад
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Other Low Power Design Techniques
Просмотров 21 тыс.7 лет назад
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Gate Level Design for Low Power (Part 2)
Просмотров 18 тыс.7 лет назад
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Gate Level Design for Low Power (Part 1)
Просмотров 27 тыс.7 лет назад
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Techniques to Reduce Power
Просмотров 71 тыс.7 лет назад
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Low Power VLSI Design
Просмотров 88 тыс.7 лет назад
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Design for Testability
Просмотров 111 тыс.7 лет назад
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Test Pattern Generation
Просмотров 37 тыс.7 лет назад
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Boundary Scan Standard
Просмотров 68 тыс.7 лет назад
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Built-in Self-Test (Part 1)
Просмотров 65 тыс.7 лет назад
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Built-in Self-Test (Part 2)
Просмотров 29 тыс.7 лет назад
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Fault Modeling (Part 2)
Просмотров 28 тыс.7 лет назад
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Fault Modeling (Part 1)
Просмотров 72 тыс.7 лет назад
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Fault Simulation (Part 2)
Просмотров 22 тыс.7 лет назад
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Testing of VLSI Circuits
Просмотров 48 тыс.7 лет назад
Testing of VLSI Circuits
mod09lec50
Просмотров 11 тыс.7 лет назад
mod09lec50
Fault Simulation (Part 1)
Просмотров 37 тыс.7 лет назад
Fault Simulation (Part 1)
Layout Compaction (Part 2)
Просмотров 7 тыс.7 лет назад
Layout Compaction (Part 2)
Layout Compaction (Part 1)
Просмотров 12 тыс.7 лет назад
Layout Compaction (Part 1)
Design Rule Check
Просмотров 60 тыс.7 лет назад
Design Rule Check
Interconnect Modeling (Part 2)
Просмотров 16 тыс.7 лет назад
Interconnect Modeling (Part 2)
Interconnect Modeling (Part 1)
Просмотров 32 тыс.7 лет назад
Interconnect Modeling (Part 1)
Miscellaneous Approaches to Timing Optimization
Просмотров 6 тыс.7 лет назад
Miscellaneous Approaches to Timing Optimization
Performance-Driven Design Flow
Просмотров 5 тыс.7 лет назад
Performance-Driven Design Flow
Physical Synthesis (Part 2)
Просмотров 9 тыс.7 лет назад
Physical Synthesis (Part 2)
Physical Synthesis (Part 1)
Просмотров 18 тыс.7 лет назад
Physical Synthesis (Part 1)
Timing Driven Routing
Просмотров 7 тыс.7 лет назад
Timing Driven Routing
Timing Driven Placement
Просмотров 9 тыс.7 лет назад
Timing Driven Placement
Time Closure (Part 1)
Просмотров 25 тыс.7 лет назад
Time Closure (Part 1)

Комментарии

  • @hariharakumar891
    @hariharakumar891 3 месяца назад

    Dog legs was a good one! First time seeing sir laugh :D

  • @smvlogs7878
    @smvlogs7878 4 месяца назад

    where i can find its original version

  • @Shahidsoc
    @Shahidsoc 4 месяца назад

    what is 1.2 in multiplier pipeline power equation ? @13:15

  • @Shahidsoc
    @Shahidsoc 4 месяца назад

    in xor, if two inputs stuck at 0, then these test vectors cnt find stuck at 0. as with all 111 actual input ll be 100 and out put will be 1.

  • @Shahidsoc
    @Shahidsoc 4 месяца назад

    how 690 ohm came ?

  • @Shahidsoc
    @Shahidsoc 4 месяца назад

    can any one tell what is link of multiplier and false path and XOR gate fanout and false path ?. at time 6:15 ...

  • @Shahidsoc
    @Shahidsoc 4 месяца назад

    for small violations and too many vilations ?

  • @Shahidsoc
    @Shahidsoc 4 месяца назад

    is it tool do all these things automatically or we can choose some options ?.

  • @Shahidsoc
    @Shahidsoc 4 месяца назад

    is there some options in the tool, to choose clk distribution network and for specific part of chip ?

  • @timothysimonthomas3396
    @timothysimonthomas3396 6 месяцев назад

    22:22 when FC =1, DL=0, not 1

  • @vyy3467
    @vyy3467 6 месяцев назад

    watching 6 year old video bcz tomorrow having exam😅😅

  • @sdeepak6555
    @sdeepak6555 6 месяцев назад

    Very useful lecture.. thanks for uploading!

  • @sdeepak6555
    @sdeepak6555 6 месяцев назад

    A & B techniques are valid , but A is a subset of B...But the problem is example given in C isn't practical...depending on whether Si or Sj being the initial state the other wouldn't exist

  • @shrikanthramanagara2382
    @shrikanthramanagara2382 7 месяцев назад

  • @pavankulkarni1739
    @pavankulkarni1739 7 месяцев назад

    so in CTS spec file we give target skew , is that local skew or global skew ?

  • @user-no1xq1ej4h
    @user-no1xq1ej4h 7 месяцев назад

    What is the tool used for generating test patterns in practical

  • @omaralmatov
    @omaralmatov 7 месяцев назад

    very helpful! thank you

  • @avnishpanchal4368
    @avnishpanchal4368 8 месяцев назад

    Sir please send me contact no

  • @kabandajamir9844
    @kabandajamir9844 9 месяцев назад

    The world's best teacher thanks sir

  • @kabandajamir9844
    @kabandajamir9844 9 месяцев назад

    So nice thanks sir

  • @soniamai8243
    @soniamai8243 9 месяцев назад

    thank you Sir for your good content.

  • @QuoteTopia
    @QuoteTopia 9 месяцев назад

    This is for which year in ECE?

    • @CB_2020
      @CB_2020 9 месяцев назад

      Year 4

  • @BonBonShrimp
    @BonBonShrimp 10 месяцев назад

    The whole series is wonderful. I'm so lucky I stumbled upon these lectures. Dr Sengupta is a GREAT teacher. Not only are the explanations great, but the way he builds up a given topic by explaining what it is and what's its use (before explaining how it's done), deserves special mention.

  • @SagarKumar-lc4cl
    @SagarKumar-lc4cl 10 месяцев назад

    Lec 63

  • @SagarKumar-lc4cl
    @SagarKumar-lc4cl 10 месяцев назад

    lec-62

  • @adarshytc
    @adarshytc 10 месяцев назад

    Thank you sir, for great effort

  • @adarshytc
    @adarshytc 11 месяцев назад

    I think Lg is wrong at 18:16

  • @resonite1352
    @resonite1352 11 месяцев назад

    Please shere the PPT also ??

  • @ash6617
    @ash6617 11 месяцев назад

    Sir u explained NOR gate schematics for the NAND gate..

  • @nitinshrinivas1831
    @nitinshrinivas1831 Год назад

    Differential Fault Simulation?

  • @DownJeans641
    @DownJeans641 Год назад

    Sir why can't you explain in simple words

  • @lakshmi-kb4ww
    @lakshmi-kb4ww Год назад

    Thankyou so much sir. Great explanation

  • @Jamboreeni
    @Jamboreeni Год назад

    @12:40 V0 - V3 it should be W23

  • @raghavdubey9138
    @raghavdubey9138 Год назад

    sir, that is CMOS NOR gate ... not a NAND gate

  • @akashashok5478
    @akashashok5478 Год назад

    Shouldn't the select line for the MUX at 7:56 have a frequency of fref/2 for correct operation?

  • @surajnayak618
    @surajnayak618 Год назад

    Thank you so much your teaching style is awesome. Everyone can easily understood

  • @akashashok5478
    @akashashok5478 Год назад

    In the fault for MUX shouldn't it be ((La0 ∩ Ls') U (Ls ∩ La1)) U {F/0} to ensure that fault does not occur on the select line when fault occurs on A0 and A0 is selected?

  • @anjalianand9359
    @anjalianand9359 Год назад

    because of you people we student can survive in our colleges ............thankyou so much sir for everything .🤩🤩😊

  • @akashashok5478
    @akashashok5478 Год назад

    What are Rint and Rtr in the cascaded buffers section?

  • @mohamedsammany3883
    @mohamedsammany3883 Год назад

    Hi sir. I have a question about abutted Floorplanning

  • @ritampal3393
    @ritampal3393 Год назад

    thank you sir for your helpful content. this helped a lot in our final year semester exam

  • @dadashri
    @dadashri Год назад

    Subtitles in Gujarati Language is of some other video.

  • @hardiksarraf1221
    @hardiksarraf1221 Год назад

    Thank you very much for your videos

  • @akashashok5478
    @akashashok5478 Год назад

    In the nine zone method there seem to be only eight zones. Can someone explain how the ninth zone came?

  • @himadrianjoy9782
    @himadrianjoy9782 Год назад

    great video

  • @metigsnv2611
    @metigsnv2611 Год назад

    thank you so much 🙏🏽 this was very helpful and clear

  • @prachetbhattacharya8222
    @prachetbhattacharya8222 Год назад

    23:10 ijH representation is correct?.. isn't j must be on top

  • @embeddedenthusiast7121
    @embeddedenthusiast7121 Год назад

    Thank you professor

  • @socialogic9777
    @socialogic9777 Год назад

    At 7:02 , in the objective it should be - minimize the number of composite nets, then only no. of tracks will reduce and channel height will reduce.

  • @socialogic9777
    @socialogic9777 Год назад

    what a line - "as if a wavefront is emanating"😇